Integrated semiconductor memory devices have been increasingly demanded to have larger capacity, operate at reduced power levels and be more readily fabricated with reduced production costs. In planar semiconductor memory devices, the integration density may be mainly determined by a planar area that a unit memory cell occupies. Thus, various process technologies for forming fine patterns have been continuously developed to increase the integration density of planar semiconductor memory devices. However, there may be some limitations in developing the process technologies for forming fine patterns. For example, high cost equipment or apparatus may be required to form the fine patterns. In addition, it may be difficult to realize the fine patterns even with the high cost equipments or apparatus.
More recently, semiconductor memory devices including memory cells arrayed in a vertical direction have been proposed to increase the integration density thereof. Nevertheless, new processes which are capable of reducing the bit cost and realizing reliable products are still required for successful mass production of the semiconductor memory devices including memory cells arrayed in a vertical direction.